When integrated circuits are manufactured, they are tested for various operating characteristics such as response time and tolerance to noise. In one method of testing an integrated circuit, and in particular, a memory chip, an external testing device writes a predetermined bit pattern in a selected location of the memory. Once written, the testing device reads back the bit pattern for verification. This is a rather slow process, however, since the testing device can only test a few bits at a time. For example, in a 1M.times.4 (1 megabit by 4 bits) memory chip, the testing device can test only 4 bits at a time in a normal operational mode. To speed up this testing process, a super-voltage circuit is used to place the memory chip into a super-voltage test mode for more efficient testing of the memory. For example, in the same 1M.times.4 memory chip, the super-voltage test mode may allow testing of 16 bits at a time. In practice, both the super-voltage test mode and normal operational mode are used to more completely test the memory chip.
The super-voltage circuit is formed on the same memory chip and comprises a sensing circuit, and an output circuit. Typically, the input of the super-voltage circuit is coupled to one of the external pins of the memory chip such as an address line or any other suitable external pin. To place the memory chip into the super-voltage test mode, the testing device applies a "super-voltage" on the selected external pin. The super-voltage is typically higher than the voltage of either a logic high signal or a logic low signal. For a 5 volt IC device, for example, the super-voltage may be 8 volts or more while the logic high voltage may be in the range of 2.4 volts to 6 volts, and the logic low voltage may be in the range of -1 volts to 0.8 volts.
When the testing device applies the super-voltage to the selected pin of the memory chip, the sensing circuit senses the super-voltage on the pin and switches its output high. In response, the output circuit switches its output to logic low signifying that the memory chip is now in the super-voltage test mode. To terminate the super-voltage test mode, the testing device removes the super-voltage from the memory chip. The sensing circuit senses the drop in the input and pulls its output low through its pull-down circuit. The pull-down circuit generally includes a pair of long L transistors designed to minimize the current drain of the super-voltage circuit. Due to these long-channel transistors, the sensing circuit takes a relatively long time to switch its output low. In one embodiment, for example, it may take approximately 150 nanoseconds to switch the output of the sensing circuit to logic low. In response to the logic low output after the 150 nanoseconds delay, the output circuit resets its output to logic high signifying that the memory chip is no longer in the super-voltage test mode.
The switching delay of the sensing circuit means that the memory chip is erroneously in the super-voltage test mode for 150 nanoseconds after the super-voltage is removed. Consequently, the testing device needs to be programmed to wait during the switching delay period before the memory chip can subsequently be tested in the normal mode.
Thus, it is desirable to provide a super-voltage circuit with a fast reset capability to improve the speed of testing memory chips.